EDN

Synopsys STAR Memory System Multi-Memory Bus Processor Enables 10 Percent Die Size Reduction for Marvell SoC

Marvell achieved silicon success for networking SoC using the multi-memory bus (MMB) processor in the Synopsys DesignWare STAR Memory System for embedded test and repair Reduced area and power with a ...
ExtremeTech

The future of AMD's Fusion APUs: Kaveri will fully share memory between CPU and GPU

AMD is hosting its Fusion Developer Summit this week, and the overarching theme is heterogeneous computing and the convergence of the CPU and GPU. Is shared memory and true heterogeneous computing the ...
Semiconductor Engineering

Automation Of Shared Bus Memory Test With Tessent MemoryBIST

Memory-heavy IPs for these applications are optimized for high performance, and they will often have a single access point for testing the memories. Tessent MemoryBIST provides an out-of-the-box ...
Design-Reuse

Synopsys STAR Memory System Multi-Memory Bus Processor Enables 10 Percent Die Size Reduction for Marvell SoC

MOUNTAIN VIEW, Calif., Oct. 21, 2014 -- Synopsys, Inc. (Nasdaq:SNPS), a global leader providing software, IP and services used to accelerate innovation in chips and electronic systems, today announced ...