EDN

How to Read Data Sheets: Logic Timing (Part 3, Flip-Flops)

The JK flip-flop augments the behavior of the SR flip-flop (J = Set, K = Reset) by interpreting the J = K = 1 condition as a “flip” or toggle command. In my previous column, we introduced latches and ...
EDN

How to Read Data Sheets: Logic Timing (Part 4)

Now that we’ve introduced a JK flip-flop, let’s look at some circuits that we can create using it as the core element, including the T and D flip-flops. In my previous column, we started to look at ...
Embedded

Static timing analysis: bridging the gap between simulation and silicon

Static Timing Analysis (STA) not only acts as a connecting link between backend and frontend design activities, but more importantly helps in bridging the gap between simulation and silicon. STA is ...