EDN

Gate level simulations: verification flow and challenges

Simulations are an important part of the verification cycle in the process of hardware designing. It can be performed at varying degrees of physical abstraction: In many companies RTL simulations is ...
Semiconductor Engineering

Gate-Level Simulation Methodology

The increase in design sizes and the complexity of timing checks at 40nm technology nodes and below is responsible for longer run times, high memory requirements, and the need for a growing set of ...
EDN

Reuse UVM RTL verification tests for gate level simulation

When we verify a System on Chip (SoC) that embeds microprocessors with several digital peripherals, and possibly analog blocks as well, we want to check all the implemented features and possible ...
Semiconductor Engineering

Writing Reusable UPF For RTL And Gate-Level Low Power Verification

The Unified Power Format (UPF) is used to specify the power intent of a design. Once written, the UPF file is applied at every stage of the design cycle — starting with the RTL, then the gate-level, ...
Design-Reuse

Accurate System Level Power Estimation through Fast Gate-Level Power Characterization

Low power consumption is becoming a critical factor for System-on-a-Chip (SoC) designs. System level power estimation for SoCs has gained importance with the increase of SoC design complexity. This ...
Electronic Design

How to Become an RTL Simulation Expert vs. Hardware Emulation Expert

In Part 1, we reviewed the process of designing a modern hardware emulation platform. Here, we’ll look at the skills and training that are necessary to become a simulation expert and an emulation ...