EDN

Open-source VHDL compiler takes fresh approach

SANTA CRUZ, Calif. — An open-source VHDL simulator, called GHDL, takes a different approach from other free VHDL offerings by serving as a front end to the Gnu Compiler Collection (GCC) suite. GHDL ...
EDN

System Compiler Adds Support for Mixed-Language Simulation with Verilog and VHDL

San Jose, CA – February 20, 2001 – C Level Design, Inc. today announced a fully automated Verilog Programming Language Interface (PLI) and VHDL Foreign Language Interface (FLI) code generators to ...
Yahoo Finance

Tabula Adds SystemVerilog Support to Stylus Compiler With Verific Design Automation Parser

ALAMEDA, CA--(Marketwired - Aug 13, 2013) - Verific Design Automation (www.verific.com), provider of SystemVerilog, Verilog and VHDL parsers, today announced that Tabula (www.tabula.com) has added ...
Electronic Design

EDA Update: C-To-VHDL High-Level Synthesis Tool

A C-TO-VHDL high-level synthesis tool is now downloadable from the Center for Embedded Computing Systems of the University of California, Irvine. Called SPARK, it takes the behavior of an application ...
Design-Reuse

From Behavioral to RTL Design Flow in SystemC

This paper reports the scientific collaboration between LLR and PROSILOG. The aim of this collaboration was to show the possibility to quickly implement a system into a FPGA, using SystemC 4 as the ...
Design-Reuse

PROGRAMMABLE LOGIC: Compiler turns FPGAs into supercomputers

Santa Cruz, Calif. — Scientists, engineers and software developers who know nothing about chip design can now compile high-performance computing applications into FPGAs, according to startup ...